The following code is to be executed on a processor with 32 architectural registers. The processor is able to issue instructions out-of-order. The processor is a single

18.
Question 18
The following code is to be
executed on a processor with 32 architectural registers. The processor is able to issue instructions
out-of-order. The processor is a single
issue machine. The processor has
different functional unit latencies with multiply instructions having a latency
of 4 cycles, ALU operations having a latency of 1 cycles, and loads and stores
having a latency of 2 cycles. The
processor stalls on WAW and WAR dependencies.
Pretend that you are the compiler and perform changes to the following
code to increase the performance of the code when executing on this out-of-order
processor. Assume that all registers not
used are free to be used by the compiler.

Problem 18 Code Sequence:

Which of the following code sequences would increase the performance of the code on this OoO processor? Select all that apply.

10 points

MUL R5, R6, R7

ADD R8, R5, R6

MUL R18, R13, R8

SW R12, 0(R18)

SUB R18, R6, R4

MUL R17, R18, R15

ADDIU R15, R5, 1

MUL R5, R6, R7

ADD R8, R5, R6

MUL R18, R13, R8

SW R12, 0(R18)

SUB R10, R6, R4

MUL R17, R10, R15

ADDIU R19, R5, 1

MUL R5, R6, R7

ADD R8, R5, R6

MUL R10, R13, R8

SW R12, 0(R10)

SUB R18, R6, R4

MUL R17, R18, R15

ADDIU R19, R5, 1

MUL R19, R6, R7

ADD R8, R19, R6

MUL R10, R13, R8

SW R12, 0(R10)

SUB R10, R6, R4

MUL R17, R10, R15

ADDIU R15, R19, 1