19.
Question 19
For questions 17 through 19, consider the following instruction sequence table:
There are four processors executing the code as interleaved below. Assume a 128-byte cache line (block size). Assume all cores contain a direct mapped data cache of size 2KB.
Questions 17 through 19 will ask about the resulting state table of the following task:.
Which of the following time do the cache conflict miss happen? Check all that apply
4 points
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14