In a pipelined processor, a single instruction takes the following synchronous exceptions (interrupts): Divide-by-Zero fault and Invalid Opcode. What should the interrupt cause be loaded with?

5.
Question 5
In a
pipelined processor, a single instruction takes the following synchronous
exceptions (interrupts): Divide-by-Zero fault and Invalid Opcode. What should the interrupt cause be loaded
with?

8 points

• Bad trap
• Invalid opcode
• Divide-by-zero
• TLB miss
• The faulting PC